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Analytic modeling of breakdown voltage shift in the CMOS buried multiple junction detector

Thais Luana Vidal de Negreiros da Silva Pascal Kleimann 1 Patrick Pittet 2 Guo-Neng Lu 2 
1 INL - LOCI - INL - Lab-On-Chip et Instrumentation
INL - Institut des Nanotechnologies de Lyon
2 INL - CSH - INL - Conception de Systèmes Hétérogènes
INL - Institut des Nanotechnologies de Lyon
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https://hal-univ-lyon1.archives-ouvertes.fr/hal-02463250
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Submitted on : Tuesday, December 21, 2021 - 10:59:05 AM
Last modification on : Saturday, September 24, 2022 - 2:58:04 PM
Long-term archiving on: : Wednesday, March 23, 2022 - 9:23:46 AM

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Thais Luana Vidal de Negreiros da Silva, Pascal Kleimann, Patrick Pittet, Guo-Neng Lu. Analytic modeling of breakdown voltage shift in the CMOS buried multiple junction detector. Solid-State Electronics, 2020, 164, pp.107682. ⟨10.1016/j.sse.2019.107682⟩. ⟨hal-02463250⟩

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